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| 1994 the m pd78c14(a) is a single-chip, cmos 8-bit microcontroller in which a 16-bit alu, a rom, a ram, an a/d converter, a multifunction timer/event counter, and a serial interface are all integrated. moreover, a 48-kbyte external expansion memory (rom/ram) can be connected. since the m pd78c14(a) uses the cmos construction, its operations are performed with low power consumption. by using the standby function, functions such as data retention are performed with lower power consumption. for details on functions, refer to the users manual listed below. please read it before starting design work. 87ad series m pd78c18 users manual: ieu-1314 features high reliability as compared with m pd78c14 159 instructions: 87ad instruction set multiply and divide instructions, 16-bit arithmetic operation instructions instruction cycle: 0.8 m s at 15 mhz internal rom: 16384 w x 8 internal ram: 256 w x 8 direct addressing to an external memory (rom/ram) up to 64 kbytes highly accurate 8-bit a/d converter: eight analog inputs general-purpose serial interface: asynchronous, synchronous, and i/o interface modes multifunction 16-bit timer/event counter two 8-bit timers i/o lines: 44 interrupt functions: three external, eight internal ? non-maskable interrupt: 1 ? maskable interrupts: 10 zero-cross detection function (two inputs) standby functions: halt mode, hardware/software stop mode ordering information part number package quality grade m pD78C14G(a)-xxx-36 64-pin plastic quip special m pD78C14Gf(a)-xxx-3be 64-pin plastic qfp (14 x 20 mm) special m pd78c14l(a)-xxx 68-pin plastic qfj (950 x 950 mil) special remark xxx is a rom code suffix. document no. ic-2813b (o.d. no. ic-8242b) date published may 1995 p printed in japan m pd78c14(a) mos integrated circuit 8-bit single-chip microcontroller (with a/d converter) please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. 1991 h the mark shows revised points. * data sheet the information in this document is subject to change without notice.
2 m pd78c14(a) pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/txd pc1/rxd pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 nmi int1 mode1 reset mode0 x2 x1 v ss pb0 pc2/sck 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 9 19 v dd stop pd7 pd6 pd5 pd4 pd3 pd2 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 wr rd av dd v aref an7 an6 an5 an4 an3 an2 an1 an0 av ss pd1 ale 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 56 46 pD78C14G(a)-xxx-36 m pd2 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd v aref an7 an6 an5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/txd pc1/rxd pc2/sck pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 nmi pd3 52 pd4 53 pd5 54 pd6 55 pd7 56 stop 57 v dd 58 pa0 59 pa1 60 pa2 61 pa3 62 pa4 63 pa5 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1718 19 51 50 49 48 47 46 454443 42 41 40 39 38 37 36 35 34 33 an4 an3 an2 an1 an0 av ss v ss x1 x2 mode0 reset mode1 int1 32 31 30 29 28 27 26 25 24 23 22 21 20 m pD78C14Gf(a)-xxx-3be pin configuration (top view) m pd78c14(a) 3 ic pa6 pa5 pa4 pa3 pa2 pa1 pa0 v dd stop pd7 pd6 pd5 pd4 pd3 pd2 ic pc7/co1 nmi int1 mode1 reset mode0 x2 x1 v ss av ss an0 an1 an2 an3 an4 an5 an6 pa7 10 pb0 11 pb1 12 pb2 13 pb3 14 pb4 15 pb5 16 pb6 17 pb7 18 pc0/txd 19 pc1/rxd 20 pc2/sck 21 pc3/int2 22 2728 29 30 3132 33 34 35 36 37 38 39 4041 42 43 98765432 168 67 66 6564 63 62 61 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd 60 59 58 57 56 55 54 53 52 51 50 49 48 m pd78c14l(a)-xxx ic 23 pc4/to 24 pc5/ci 25 pc6/co0 26 av dd 47 ic 46 v aref 45 an7 44 4 m pd78c14(a) block diagram pf7-0/ab15-8 pd7-0/ad7-0 pc7-0 pb7-0 pa7-0 8 8 8 8 8 port a port b port c port d port f 8 8 8 8 8 8 8 8 8 16 16 6 8 16 14 16 16 16 16 8 8 8 8 8 8 8/16 8 inst.reg inst. decoder data memory (256-byte) program memory (16 k-byte) main g.r alt g.r internal data bus alu (8/16) psw latch latch 8 standby control system control read/write control v ss v dd stop reset mode1 mode0 ale wr rd latch inc/dec pc sp ea v b d h a c e l ea' v' b' d' h' a' c' e' l' buffer osc serial i/o int. control timer timer event counter a/d converter x1 x2 pc0/txd pc1/rxd pc2/sck nmi int1 pc3/int2/ti pc4/to pc5/ci av ss pc7/co1 pc6/co0 an7-0 8 v aref v dd note note data memory can only be used when rae bit of mm register is set to 1. external memory is necessary when 0 is set. 4 m pd78c14(a) 5 contents 1. differences between m pd78c14(a) and m pd78c14 ...................................................6 2. pin functions ................................................................................................................ ......7 2.1 pin function list ........................................................................................................... ..............7 2.2 pin input/output circuits ................................................................................................... ........9 2.3 recommended connections for unused pins....................................................................... 13 3. instruction set .............................................................................................................. ..14 3.1 operand expression format/description method .................................................................14 3.2 instruction code description ................................................................................................ ..16 3.3 instruction execution time.................................................................................................. ....17 4. list of mode registers .................................................................................................29 5. electrical specifications ..........................................................................................30 6. characteristic curves (reference value) ...................................................................41 7. package drawings .........................................................................................................44 8. recommended soldering conditions .....................................................................47 appendix development tools ............................................................................................49 6 m pd78c14(a) 1. differences between m pd78c14(a) and m pd78c14 part number m pd78c14(a) m pd78c14 item quality grade special standard electrical input leakage current input leakage current specifications (an7-0; 1 m a (max.) an7-0; 10 m a (max.) package ? 64-pin plastic quip ? 64-pin plastic shrink dip ? 64-pin plastic qfp ? 64-pin plastic quip (14 x 20 mm, thickness: 2.05 mm) ? 64-pin plastic quip (straight) ? 68-pin plastic qfj ? 64-pin plastic qfp (14 x 20 mm, thickness: 2.05 mm) ? 64-pin plastic qfp (14 x 20 mm, thickness: 2.70 mm) ? 68-pin plastic qfj m pd78c14(a) 7 2. pin functions 2.1 pin function list pin input/output function pa7-pa0 input/output these 8 pins constitute an 8-bit i/o port and input/output can be specified in bit (port a) units. pb7-pb0 input/output these 8 pins constitute an 8-bit i/o port and input/output can be specified in bit (port b) units. pc0/txd input/output, port c transmit data output these 8 pins constitute an 8-bit i/o this pin outputs serial data. pc1/rxd input/output, port and input/output can be specified receive data input in bit units. this pin inputs serial data. pc2/sck input/output, serial clock input/output this pin inputs/outputs serial clock. it be- comes an output pin when an internal clock is used or an input pin when an external clock is used. pc3/int2/ti input/output, interrupt request/timer input input, input this pin inputs edge triggering (falling edge) maskable interrupt or external clock for timer. this pin is also shared with zero-cross detection pin for ac input. pc4/to input/output, timer output output this pin outputs square waves in which one cycle of the internal clock forms a half cycle, indicating the timers counting time. pc5/ci input/output, counter input input this pin inputs external pulse for timer/ event counter. pc6/co0 input/output, counter output 0,1 pc7/co1 output this pin outputs programmable square wave by timer/event counter. pd7-pd0/ input/output, port d address/data bus ad7-ad0 input/output these 8 pins constitute an 8-bit i/o these pins function as multiplexed port and input/output can be address/data bus when using an specified in byte units. external memory. pf7-pf0/ input/output, port f address bus ab15-ab8 output these 8 pins constitute an 8-bit i/o these pins function as address bus when port and input/output can be specified using an external memory. in bit units. wr output this is a strobe signal output to write data in external memory. this signal (write becomes high level except during the data write machine cycle for external memory. strobe) this signal becomes output high impedance when the reset signal is low or in the hardware stop mode. 8 m pd78c14(a) (continued) pin input/output function rd output this is a strobe signal output to read data from external memory. this signal (read becomes high level except during the data read machine cycle for external memory. strobe) this signal becomes output high impedance when the reset signal is low or in the hardware stop mode. ale output this is a strobe signal to externally latch the low-order address information (address output to pins pd7-pd0 to access the external memory. this signal becomes latch output high impedance when the reset signal is low or in the hardware stop enable) mode. mode0 input/output set the mode0 pin to 0 (low level) and mode1 pin to 1 (high level) note . mode1 when both pins mode0 and mode1 are set to 1 note , these pins synchronize to (mode) the ale and a control signal is output. nmi input this pin inputs the edge triggering (falling edge) nonmaskable interrupt. (non- maskable interrupt) int1 input this pin inputs edge triggering (rising edge) maskable interrupt. this pin is also (interrupt shared with zero-cross detection pin for ac input. request) an7-an0 input these eight pins input analog signals for the a/d converter. pins an7-an4 can (analog be used as edge detection (falling edge) input. input) v aref input this pin inputs the reference voltage for the a/d converter and controls the (reference operation for the a/d converter. voltage) av dd power supply pin for the a/d converter (analog v dd ) av ss ground pin for the a/d converter (analog v ss ) x1, x2 these are crystal connecting pins for the system clock oscillation. when a clock (crystal) is externally supplied, input it through pin x1. input the clock to x1 and its reverse phase to x2. reset input this pin inputs the active-low reset input signal. (reset) stop input this pin inputs control signal of the hardware stop mode. when the low level (stop) of this signal is input, the oscillator stops to operate. v dd positive power supply pin v ss ground pin note pull-up with the following external resistor: 4 (k w ) r 0.4 t cyc (k w )t cyc (unit: ns) example 4 (k w ) r 26 (k w ): t cyc = 66 (ns) at 15 mhz 4 (k w ) r 33 (k w ): t cyc = 83 (ns) at 12 mhz m pd78c14(a) 9 2.2 pin input/output circuits schematic input/output circuits of the pins are shown in table 2-1 and figures from (1) to (11). table 2-1. name of type no. pin type no. pin type no. pa0-7 5 reset 2 pb0-7 5 rd 4 pc0-1 5 wr 4 pc2/sck 8 ale 4 pc3/int2 10 stop 2 pc4-7 5 mode0 11 pd0-7 5 mode1 11 pf0-7 5 an0-3 7 nmi 2 an4-7 12 int1 9 v aref 13 10 m pd78c14(a) type 4 in/out output data output disable type 1 in p-ch v dd out n-ch output data output disable n-ch p-ch v dd in (1) type 1 (2) type 2 (3) type 4 (4) type 5 m pd78c14(a) 11 in/out type 5 type 9 n-ch n-ch mcc output data output disable self bias enable in/out type 5 type 2 output data output disable n-ch n-ch mcc + av ss av dd av ss av dd in p-ch n-ch sampling c reference voltage (from voltage tap of serial resistor string) (5) type 7 (6) type 8 (7) type 9 (8) type 10 in type 1 self bias enable data 12 m pd78c14(a) type 1 in av ss stop mode p-ch (9) type 11 (10) type 12 (11) type 13 type 7 type 2 in edge detection circuit output data type 1 n-ch in/out m pd78c14(a) 13 2.3 recommended connections for unused pins pin recommended connection pa7-0 pb7-0 pc7-0 connect to v dd or v ss via resistor. pd7-0 pf7-0 rd wr leave unconnected. ale stop v dd int1, nmi connect to v dd or v ss . av dd connect to v dd . v aref connect to v ss . av ss an7-0 connect to av ss or av dd . 14 m pd78c14(a) 3. instruction set 3.1 operand expression format/description method expression format description method r v, a, b, c, d, e, h, l r1 eah, eal, b, c, d, e, h, l r2 a, b, c sr pa, pb, pc, pd, pf, mkh, mkl, anm, smh, sml, eom, etmm, tmm, mm, mcc, ma, mb, mc, mf, txb, tm0, tm1, zcm sr1 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm, rxb, cr0, cr1, cr2, cr3 sr2 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm sr3 etm0, etm1 sr4 ecnt, ecpt rp sp, b, d, h rp1 v, b, d, h, ea rp2 sp, b, d, h, ea rp3 b, d, h rpa b, d, h, d+, h+, dC, hC rpa1 b, d, h rpa2 b, d, h, d+, h+, dC, hC, d+byte, h+a, h+b, h+ea, h+byte rpa3 d, h, d++, h++, d+byte, h+a, h+b, h+ea, h+byte wa 8-bit immediate data word 16-bit immediate data byte 8-bit immediate data bit 3-bit immediate data f cy, hc, z irf nmi note , ft0, ft1, f1, f2, fe0, fe1, fein, fad, fsr, fst, er, ov, an4, an5, an6, an7, sb note nmi can be also described as fnmi. m pd78c14(a) 15 remarks 1. sr to sr4 (special register) 2. rp to rp3 (register pair) 4. f (flag) pa : port a etmm : timer/event sp : stack pointer cy : carry pb : port b counter mode b : bc hc : half carry pc : port c eom : timer/event d : de z : zero pd : port d counter output h : hl pf : port f mode v : va 5. irf (interrupt flag) ma : mode a anm : a/d channel mode ea : extended nmi : nmi input mb : mode b cr0 : a/d conversion accumulator ft0 : intft0 mc : mode c to result 0 to 3 ft1 : intft1 mcc : mode control c cr3 3. rpa to rpa3 (rp addressing) f1 : intf1 mf : mode f txb : tx buffer b : (bc) f2 : intf2 mm : memory mapping rxb : rx buffer d : (de) fe0 : intfe0 tm0 : timer reg0 smh : serial mode high h : (hl) fe1 : intfe1 tm1 : timer reg1 sml : serial mode low d+ : (de)+ fein: intfein tmm : timer mode mkh : mask high h+ : (hl)+ fad : intfad etm0 : timer/event mkl : mask low dC : (de)C fsr : intfsr counter reg0 zcm : zero cross mode hC : (hl)C fst : intfst etm1 : timer/event d++ : (de)++ er : error counter reg1 h++ : (hl)++ ov : overflow ecnt : timer/event d+byte : (de+byte) an4 : analog input counter upcounter h+a : (hl+a) to 4 to 7 ecpt : timer/event h+b : (hl+b) an7 counter capture h+ea : (hl+ea) sb : standby h+byte : (hl+byte) 16 m pd78c14(a) r r 2 r 1 r 0 reg 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v a b c d e h l r1 t 2 t 1 t 0 reg 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 eah eal b c d e h l rpa a 3 a 2 a 1 addressing 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 (bc) (de) (hl) (de) + (hl) + (de) (hl) (de+byte) (hl+a) (hl+b) (hl+ea) (hl+byte) a 0 0 1 0 1 0 1 0 1 1 0 1 0 1 rpa rpa1 rpa2 r2 sr s 5 s 4 s 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 s 2 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 special-reg pa pb pc pd pf mkh mkl anm smh sml eom etmm tmm mm mcc ma mb mc mf txb rxb tm0 tm1 cr0 cr1 cr2 cr3 zcm s 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 s 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 sr1 sr2 r rpa3 c 3 c 2 c 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 c 0 0 1 0 1 1 0 1 0 1 addressing (de) (hl) (de) ++ (hl) ++ (de+byte) (hl+a) (hl+b) (hl+ea) (hl+byte) irf i 3 i 2 i 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 i 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 intf nmi ft0 ft1 f1 f2 fe0 fe1 fein fad fsr fst er ov an4 an5 an6 an7 sb i 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 sr3 u 0 0 1 special-reg etm0 etm1 sr4 v 0 0 1 special-reg ecnt ecpt p 2 p 1 p 0 reg-pair 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 sp bc de hl ea rp q 2 q 1 q 0 reg-pair 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 va bc de hl ea rp1 f 2 f 1 f 0 flag 0 0 0 1 0 1 1 0 0 0 1 0 cy hc z f rp rp2 rp3 sr 3.2 instruction code description m pd78c14(a) 17 3.3 instruction execution time in the following table, one state consists of three clock cycles. so, when the 15 mhz clock is used, one state becomes 200 ns (= 3 x 1/15 m s). execution time of the 4-state instruction, the shortest instruction, becomes 0.8 m s. 18 m pd78c14(a) instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 r1, a 0 0 0 1 1 t 2 t 1 t 0 4 r1 a a, r1 0 0 0 0 1 t 2 t 1 t 0 4 a r1 * * 1 1 s 5 s 4 s 3 s 2 s 1 s 0 sr, a 0 1 0 0 1 1 0 1 10 sr a mov a, sr1 r, word word, r 1 1 s 5 s 4 s 3 s 2 s 1 s 0 0 1 0 0 1 1 0 0 0 1 1 0 1 r 2 r 1 r 0 0 1 1 1 0 0 0 0 0 1 1 1 1 r 2 r 1 r 0 0 1 1 1 0 0 0 0 data low adrs low adrs high adrs high adrs 10 a sr1 17 r (word) 17 (word) r 8-bit data transfer 16-bit data transfer mvi mviw mvix staw ldaw stax ldax exx exa exh block dmov * * * * * * * r, byte 0 1 1 0 1 r 2 r 1 r 0 sr2, byte 0 1 1 0 0 1 0 0 wa, byte 0 1 1 1 0 0 0 1 rpa1, byte 0 1 0 0 1 0 a 1 a 0 0 1 1 0 0 0 1 1 wa 0 0 0 0 0 0 0 1 wa a 3 0 1 1 1 a 2 a 1 a 0 rpa2 a 3 0 1 0 1 a 2 a 1 a 0 rpa2 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 p 1 p 0 1 0 1 0 0 1 p 1 p 0 s 3 0 0 0 0 s 2 s 1 s 0 offset data offset offset data data note 1 note 1 data data 7 14 13 10 10 10 7/13 7/13 4 4 4 13 (c+1) 4 4 note 3 note 3 r byte sr2 byte (v. wa) byte (rpa1) byte (v. wa) a a (v. wa) (rpa2) a a (rpa2) b b', c c', d d' e e', h h', l l' v, a v', a', ea ea' h, l h', l' (de) + (hl) + , c c? end if borrow rp3 l eal, rp3 h eah eal rp3 l , eah rp3 h { rp3, ea ea, rp3 m pd78c14(a) 19 instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 sr3, ea 0 1 0 0 1 0 0 0 14 sr3 ea ea, sr4 1 1 0 0 0 0 0 v 0 14 ea sr4 0 0 0 1 1 1 1 0 word 0 1 1 1 0 0 0 0 20 (word) c, (word+1) b sbcd word word word 0 0 1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 low adrs high adrs 20 (word) e, (word+1) d 20 (word) l, (word+1) h 20 (word) sp l , (word+1) sp h 16-bit data transfer 8-bit arithmetic operation (register) steax lded lhld lspd ldeax push pop lxi table add adc * rpa3 0 1 0 0 1 0 0 0 word 0 1 1 1 0 0 0 0 word word word 0 1 0 0 1 0 0 0 rpa3 1 0 1 1 0 q 2 q 1 q 0 rp1 1 0 1 0 0 q 2 q 1 q 0 rp1 0 p 2 p 1 p 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 low byte data 14/20 20 20 20 20 14/20 13 10 10 17 8 8 8 8 note 3 (rpa3) eal, (rpa3+1) eah c (word), b (word+1) e (word), d (word+1) l (word), h (word+1) sp l (word), sp h (word+1) eal (rpa3), eah (rpa3+1) (sp?) rp1 h , (sp?) rp1 l sp sp? rp1 l (sp), rp1 h (sp+1) sp sp+2 rp2 word c (pc+3+a) b (pc+3+a+1) a a+r r r+a a a+r+cy r r+a+cy dmov sded shld sspd lbcd rp2, word a, r r, a a, r r, a 1 1 0 1 0 0 1 u 0 1 1 0 0 0 r 2 r 1 r 0 1 0 1 0 1 0 0 0 1 0 0 0 c 3 c 2 c 1 c 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 c 3 c 2 c 1 c 0 note 2 low adrs data note 2 high adrs high byte note 3 20 m pd78c14(a) instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 a, r 0 1 1 0 0 0 0 0 8 a a+r r, a 0 0 1 0 8 r r+a 1 1 1 0 a, r 8 a a? r, a a, r r, a 0 1 1 0 1 1 1 1 0 1 1 1 8 r r? 8 a a??y 8 r r??y 8-bit arithmetic operation (register) ana ora xra gta lta nea a, r r, a a, r r, a a, r r, a 1 0 0 1 0 r 2 r 1 r 0 a, r 0 0 0 1 r, a 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 a a? r r? a a r r r a a a r r r a a a r r r a a?? r?? a? r? a? r? addnc sub sbb subnb a, r a, r r, a a, r r, a 1 0 1 0 0 r 2 r 1 r 0 1 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 r 2 r 1 r 0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 r 2 r 1 r 0 no zero r, a < < > > > > no zero borrow borrow no borrow no borrow no borrow no carry no carry no borrow m pd78c14(a) 21 instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 a, r 0 1 1 0 0 0 0 0 8 a? r, a 0 1 1 1 8 r? 1 1 0 0 a, r 8 a r a, r rpa rpa 1 1 0 1 1 1 0 0 0 a 2 a 1 a 0 1 1 0 1 8 a r 11 a a+(rpa) 11 a a+(rpa)+cy 8-bit arithmetic operation (memory) sbbx anax xrax gtax ltax neax rpa rpa rpa rpa rpa rpa 1 0 0 1 0 a 2 a 1 a 0 rpa 1 0 1 0 1 a 2 a 1 a 0 rpa 1 1 0 0 1 1 0 1 1 1 1 0 11 11 11 11 11 11 11 11 11 11 11 11 11 a a+(rpa) a a?rpa) a a?rpa)?y a a?rpa) a a (rpa) a a (rpa) a a (rpa) a?rpa)? a?rpa) a?rpa) a?rpa) a (rpa) eqa ona addx addncx rpa rpa rpa rpa 1 1 1 1 1 r 2 r 1 r 0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 a 2 a 1 a 0 1 0 1 0 1 0 1 1 zero rpa < > no zero zero borrow no borrow no carry zero no borrow no zero zero zero no zero < < > < offa adcx subx subnbx orax eqax onax offax 0 1 1 1 0 0 0 0 a (rpa) < 8-bit arithmetic operation (register) 22 m pd78c14(a) instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 a, byte 0 1 0 0 0 1 1 0 7 a a+byte r, byte 0 1 1 1 0 1 0 0 11 r r+byte * * 0 1 0 0 0 r 2 r 1 r 0 sr2, byte 0 1 1 0 20 sr2 sr2+byte adi a, byte r, byte sr2, byte s 3 1 0 0 0 s 2 s 1 s 0 0 1 0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 data 7 a a+byte+cy 11 r r+byte+cy 20 sr2 sr2+byte+cy arithmetic operation of immediate data aci adinc sui sbi suinb ani * * * * * a, byte 0 0 1 0 0 1 1 0 r, byte 0 1 1 1 0 1 0 0 sr2, byte 0 1 1 0 a, byte 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 0 r, byte 0 1 1 0 sr2, byte 0 1 1 1 0 1 1 0 a, byte 0 1 1 1 0 1 0 0 r, byte 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 0 data data 7 11 20 7 11 20 7 11 20 7 11 20 7 11 a a+byte r r+byte sr2 sr2+byte a a?yte r r?yte sr2 sr2?yte a a?yte?y r r?yte?y sr2 sr2?yte?y a a?yte r r?yte sr2 sr2?yte r r byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte data data data data 0 1 0 1 0 r 2 r 1 r 0 s 3 1 0 1 0 s 2 s 1 s 0 data 0 0 1 0 0 r 2 r 1 r 0 s 3 0 1 0 0 s 2 s 1 s 0 0 1 1 0 0 r 2 r 1 r 0 s 3 1 1 0 0 s 2 s 1 s 0 0 1 1 1 0 r 2 r 1 r 0 s 3 1 1 1 0 s 2 s 1 s 0 0 0 1 1 0 r 2 r 1 r 0 s 3 0 1 1 0 s 2 s 1 s 0 0 0 0 0 1 r 2 r 1 r 0 data data data data data data no carry no borrow no carry no carry no borrow no borrow < < a a byte m pd78c14(a) 23 instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 sr2, byte 0 1 1 0 0 1 0 0 sr2 sr2 byte a, byte 0 0 0 1 0 1 1 1 a a byte * * 0 0 0 1 1 r 2 r 1 r 0 r, byte 0 1 1 1 0 1 0 0 20 r r byte ani sr2, byte a, byte r, byte s 3 0 0 1 1 s 2 s 1 s 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 data 7 sr2 sr2 byte 11 a a byte 20 arithmetic operation of immediate data ori xri gti lti nei eqi * * * * sr2, byte 0 1 1 0 a, byte 0 0 1 0 0 1 1 1 r, byte 0 1 1 1 0 1 0 0 sr2, byte 0 1 1 0 0 0 1 1 0 1 1 1 a, byte 0 1 1 1 0 1 0 0 r, byte 0 1 1 0 sr2, byte 0 1 1 0 0 1 1 1 a, byte 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 data data 7 11 20 7 11 14 7 11 a?yte? r?yte? sr2?yte? a?yte r?yte sr2?yte a?yte r?yte sr2?yte a?yte r?yte sr2?yte r, byte sr2, byte a, byte r, byte sr2, byte data data data 0 0 0 1 0 r 2 r 1 r 0 s 3 0 0 1 0 s 2 s 1 s 0 data 0 0 1 0 1 r 2 r 1 r 0 s 3 0 1 0 1 s 2 s 1 s 0 0 0 1 1 1 r 2 r 1 r 0 s 3 0 1 1 1 s 2 s 1 s 0 0 1 1 0 1 r 2 r 1 r 0 s 3 1 1 0 1 s 2 s 1 s 0 0 1 1 1 1 r 2 r 1 r 0 s 3 1 1 1 1 s 2 s 1 s 0 data data data data data zero no zero borrow < s 3 0 0 0 1 s 2 s 1 s 0 data 14 7 11 14 7 11 14 < < < < r r byte < sr2 sr2 byte < zero zero no zero no zero borrow borrow no borrow no borrow no borrow 24 m pd78c14(a) instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 a, byte 0 1 0 0 0 1 1 1 7 a byte r, byte 0 1 1 1 0 1 0 0 11 r byte * * 0 1 0 0 1 r 2 r 1 r 0 sr2, byte 0 1 1 0 14 sr2 byte oni a, byte r, byte sr2, byte s 3 1 0 0 1 s 2 s 1 s 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 7 a byte 11 r byte 14 sr2 byte arithmetic operation of immediate data offi adcw sbbw oraw ltaw onaw wa 0 1 1 1 0 1 0 0 wa wa wa wa wa wa wa data 14 14 14 14 14 14 14 14 14 14 14 14 14 14 a a+(v.wa) a a+(v.wa)+cy a a+(v.wa) a a?v.wa) a a?v.wa) a a (v.wa) a a (v.wa) a a (v.wa) a?v.wa)? a?v.wa) a?v.wa) a?v.wa) a (v.wa) wa wa wa wa wa wa data 0 1 0 1 1 r 2 r 1 r 0 s 3 1 0 1 1 s 2 s 1 s 0 data 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 data offset no zero zero no borrow no zero borrow < eqaw neaw xraw gtaw subnbw anaw addncw subw addw 1 1 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 no zero no borrow no carry no zero no zero zero zero zero < < < < < < < > > a a?v.wa)?y arithmetic operation of working register m pd78c14(a) 25 instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 wa 0 1 1 1 0 1 0 0 14 a (v.wa) wa, byte offset 19 (v.wa) (v.wa) byte wa, byte 19 (v.wa) (v.wa) byte wa, byte wa, byte wa, byte 13 (v.wa)?yte? 13 (v.wa)?yte 13 (v.wa)?yte 16-bit arithmetic operation offiw dadd daddnc esub dsub dsbb wa, byte wa, byte wa, byte ea, r2 ea, rp3 ea, rp3 1 0 1 0 ea, rp3 0 1 1 0 0 0 r 1 r 0 ea, r2 1 0 0 0 1 1 p 1 p 0 1 0 0 1 13 13 13 11 11 11 11 11 11 11 11 11 11 (v.wa)?yte (v.wa) byte (v.wa) byte ea ea+r2 ea ea+rp3 ea ea+rp3+cy ea ea+rp3 ea ea?2 ea ea?p3 ea ea?p3?y ea ea?p3 ea ea rp3 offaw oriw ltiw eqiw ea, rp3 ea, rp3 ea, rp3 ea, rp3 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 r 1 r 0 1 1 1 0 0 1 p 1 p 0 ea, rp3 < > zero borrow no borrow no carry no borrow no zero zero zero no zero < < > gtiw neiw oniw eadd dadc dsubnb dan dor 0 0 1 1 ea ea rp3 arithmetic operation of working register aniw 1 0 0 1 0 1 p 1 p 0 ea, rp3 dxr 11 ea ea rp3 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 * * * * * * * * 0 1 0 0 data offset << < 1 1 0 0 0 1 p 1 p 0 26 m pd78c14(a) instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 ea, rp3 0 1 1 1 0 1 0 0 11 ea?p3? ea, rp3 offset 11 ea?p3 ea, rp3 11 ea?p3 ea, rp3 ea, rp3 ea, rp3 11 ea?p3 11 ea rp3 11 ea rp3 decrement/increment inr inx dcr dcrw dcx daa r2 r2 r2 wa rp ea r2 wa 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 32 59 4 16 7 7 4 16 7 7 4 8 8 ea a r2 ea ea?2, r2 the remainder r2 r2+1 (v.wa) (v.wa)+1 rp rp+1 ea ea+1 r2 r2? (v.wa) (v.wa)? rp rp? ea ea? decimal adjust accumulator cy 1 dgt dne don mul rp 1 0 1 0 1 1 p 1 p 0 ea < carry borrow no borrow no zero zero zero no zero < deq doff div inrw stc clc nega cy 0 16-bit arithmetic operation dlt 0 0 1 1 1 0 1 0 8 a a+1 0 1 0 0 1 0 0 0 * * multiply/ divide other arithmetic operation 0 1 0 1 0 0 r 1 r 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 0 0 0 r 1 r 0 0 0 p 1 p 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 p 1 p 0 0 0 1 1 0 0 1 1 0 0 0 0 offset 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 r 1 r 0 1 0 1 1 carry borrow borrow m pd78c14(a) 27 instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 0 1 0 0 1 0 0 0 17 rotate left digit 17 rotate right digit r2 8 r2 m+1 r2 m , r2 0 cy, cy r2 7 r2 r2 r2 8 r2 m? r2 m , r2 7 cy, cy r2 0 8 r2 m+1 r2 m , r2 0 0, cy r2 7 8 r2 m? r2 m , r2 7 0, cy r2 0 jump drll dsll jmp jb jr jea r2 r2 ea ea ea ea word 0 0 1 0 1 0 0 1 8 8 8 8 8 8 10 4 10 10 8 16 17 r2 m+1 r2 m , r2 0 0, cy r2 7 r2 m? r2 m , r2 7 0, cy r2 0 ea n+1 ea n , ea 0 cy, cy ea 15 ea n? ea n , ea 15 cy, cy ea 0 ea n+1 ea n , ea 0 0, cy ea 15 ea n? ea n , ea 15 0, cy ea 0 pc word pc h b, pc l c pc pc+1+jdisp 1 pc pc+2+jdisp pc ea (sp?) (pc+3) h , (sp?) (pc+3) l pc word, sp sp? rld rll sll sllc word 0 0 1 1 1 0 0 0 word carry rlr slr slrc drlr call calb calf (sp?) (pc+2) h , (sp?) (pc+2) l pc h b, pc l c, sp sp? rotation shift rrd 13 (sp?) (pc+2) h , (sp?) (pc+2) l pc 15?1 00001, pc 10? fa, sp sp? * * call 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 low adrs 0 0 r 1 r 0 0 0 1 0 0 1 r 1 r 0 0 1 r 1 r 0 0 0 r 1 r 0 0 0 r 1 r 0 0 0 0 0 0 1 r 1 r 0 1 0 0 1 carry dslr jre * * word word 0 1 1 1 1 0 1 0 0 1 0 0 0 jdisp 1 fa 0 0 1 0 1 0 0 0 jdisp low adrs high adrs high adrs 0 0 0 0 28 m pd78c14(a) instruc- tion group instruction code mnemonic operand state operation skip condition b1 b2 b3 b4 1 0 0 16 (sp 1) (pc+1) h , (sp 2) (pc+1) l , pc l (128+2ta), pc h (129+2ta), sp sp 2 16 (sp 1) psw, (sp 2) (pc+1) h , (sp 3) (pc+1) l , pc 0060h, sp sp 3 word 10 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 bit, wa 10 13 10 skip if (v.wa) bit = 1 skit nop di hlt stop f f irf irf 8 8 8 8 4 4 4 12 12 skip if f = 1 skip if f = 0 skip if irf = 1, then reset irf skip if irf = 0 reset irf, if irf = 1 no operation enable interrupt disable interrupt set halt mode set stop mode calt ret reti sk uncondi- tional rets bit skn sknit skip soft1 * 1 0 1 1 1 0 1 0 0 1 0 0 1 0 0 0 (v.wa) bit = 1 ei offset 0 1 1 1 0 0 1 0 1 0 0 1 call return cpu operation 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 b 2 b 1 b 0 0 1 0 0 1 0 0 0 ta 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 i 4 i 3 i 2 i 1 i 0 0 1 1 i 4 i 3 i 2 i 1 i 0 0 0 0 0 1 f 2 f 1 f 0 0 0 0 1 f = 1 f = 0 irf = 1 irf = 0 pc l (sp), pc h (sp+1) sp sp+2 pc l (sp), pc h (sp+1), sp sp+2 pc pc+n notes 1. b2 (data) is applied for rpa2 = d + byte or h + byte. 2. b3 (data) is applied for rpa3 = d + byte or h + byte. 3. in the "state" column, data to the right of the slash applies when rpa2 or rpa3 is d + byte, h + a, h + b, h + ea, or h + byte . remark when the instructions below are skipped, the number of idle states is as listed below and differs from the number of executio n states. 1-byte instruction 2-byte (with *) 2-byte : 4-state : 7-state : 8-state 3-byte instruction (with *) 3-byte 4-byte : 10-state : 11-state : 14-state pc l (sp), pc h (sp+1) psw (sp+2), sp sp+3 m pd78c14(a) 29 4. list of mode registers name of mode register read/write function ma mode a w specifies input/output of port a in bit units mb mode b w specifies input/output of port b in bit units mcc mode control c w specifies port/control mode of port c in bit units mc mode c w specifies input/output of port c set in the port mode in bit units mm memory mapping w specifies port/expansion mode of ports d and f mf mode f w specifies input/output of port f set in the port mode in bit units tmm timer mode r/w specifies operation mode of the timer etmm timer/event w specifies operation mode of the timer event counter counter mode eom timer/event r/w controls output level of co0 and co1 counter output mode sml serial mode w specifies operation mode of the serial interface smh r/w mkl interrupt mask r/w specifies interrupt request enable/disable mkh anm a/d channel mode r/w specifies operation mode of the a/d converter zcm zero-cross mode w specifies operation mode of the zero-cross detection circuit m pd78c14(a) 30 5. electrical specifications absolute maximum ratings (t a = 25 ?c) parameter symbol test condition ratings unit power supply voltage v dd C0.5 to +7.0 v av dd av ss to v dd + 0.5 v av ss C0.5 to +0.5 v input voltage v i C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v output current low i ol all output pin 4.0 ma all output pin total 100 ma output current high i oh all output pin C2.0 ma all output pin total C50 ma a/d converter v aref C0.5 to av dd + 0.3 v reference input voltage operating ambient t a C40 to +85 ?c temperature storage temperature t stg C65 to +150 ?c caution if any of the parameters exceeds the absolute maximum ratings even for a moment, this may damage product quality. the absolute maximum ratings are values that may physically damage the product. you must use the product within the specified ratings. * m pd78c14(a) 31 oscillation characteristics (t a = C40 to +85 ?c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C 0.8 v av dd v dd , 3.4 v v aref av dd ) resonator recommended circuits parameter test conditions min. max. unit ceramic oscillation frequency (fxx) a/d converter 4 15 mhz resonator not used or crystal resonator note a/d converter 5.8 15 mhz used external x1 input frequency a/d converter 4 15 mhz clock (fx) not used a/d converter 5.8 15 mhz used x1 input 0 20 ns rise, fall time (t r , t f ) x1 input high, low 20 250 ns level width (t? h , t? l ) cautions 1. oscillator circuit should be in the nearest area from x1 and x2 pins. 2. do not place other signal lines within the area enclosed with broken lines. note for a crystal resonator, the following external capacitances are recommended: c1 = c2 = 10 pf capacitance (t a = 25 ?c, v dd = v ss = 0 v) parameter symbol test condition min. typ. max. unit input capacitance c i f c = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v 20 pf i/o capacitance c io 20 pf x1 x2 c1 c2 x1 x2 hcmos inverter m pd78c14(a) 32 dc characteristics (t a = C40 to +85 ?c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) parameter symbol test condition min. typ. max. unit input low voltage v il1 all except reset, stop, nmi, sck, int1, 0 0.8 v ti, an7 to an4 v il2 reset, stop, nmi, sck, int1, ti, an7 to an4 0 0.2v dd v input high voltage v ih1 all except reset, stop, nmi, sck, int1, 2.2 v dd v ti, an7 to an4, x1, x2 v ih2 reset, stop, nmi, sck, int1, ti, an7 to 0.8v dd v dd v an4, x1, x2 output low voltage v ol i ol = 2.0 ma 0.45 v output high voltage v oh i oh = C1.0 ma v dd C 1.0 v i oh = C100 m a v dd C 0.5 v input current i i int1 note 1 , ti (pc3) note 2 ; 0 v v i v dd 200 m a input leakage i li all except int1, ti (pc3), an7 to an0; 0 v v i v dd 10 m a current an7 to an0; 0 v v i v dd 1 m a output leakage i lo 0 v v o v dd 10 m a current av dd supply ai dd1 operation mode f xx = 15 mhz 0.5 1.3 ma current ai dd2 stop mode 10 20 m a v dd supply current i dd1 operation mode f xx = 15 mhz 16 30 ma i dd2 halt mode f xx = 15 mhz 8 15 ma data retention v dddr hardware/software stop mode 2.5 v voltage data retention i dddr hardware/software note 3 v dddr = 2.5 v 1 15 m a current stop mode v dddr = 5 v 10 % 10 50 m a notes 1. when self-bias is generated by zcm register. 2. when set in the control mode by mcc register and self-bias is generated by zcm register. 3. when self-bias is not generated. m pd78c14(a) 33 ac characteristics (t a = C40 to +85 ?c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) read/write operation: parameter symbol test condition min. max. unit x1 input cycle time t cyc 66 250 ns address setup time to ale t al f xx = 15 mhz, c l = 150 pf 30 ns address hold time after ale ? t la 35 ns address ? rd ? delay time t ar 100 ns rd ? ? address floating time t afr c l = 150 pf 20 ns address ? data input time t ad f xx = 15 mhz, cl = 150 pf 250 ns ale ? ? data input time t ldr 135 ns rd ? ? data input time t rd 120 ns ale ? ? rd ? delay time t lr 15 ns data hold time after rd t rdh c l = 150 pf 0 ns rd ? ale delay time t rl f xx = 15 mhz, c l = 150 pf 80 ns rd width low t rr data read 215 ns f xx = 15 mhz, c l = 150 pf op code fetch 415 ns f xx = 15 mhz, c l = 150 pf ale width high t ll f xx = 15 mhz, c l = 150 pf 90 ns m1 setup time to ale ? t ml f xx = 15 mhz 30 ns m1 hold time after ale ? t lm 35 ns io/m setup time to ale ? t il 30 ns io/m hold time after ale ? t li 35 ns address ? wr ? delay time t aw f xx = 15 mhz, c l = 150 pf 100 ns ale ? ? data output time t ldw 180 ns wr ? ? data output time t wd c l = 150 pf 100 ns ale ? ? wr ? delay time t lw f xx = 15 mhz, c l = 150 pf 15 ns data setup time to wr t dw 165 ns data hold time after wr t wdh 60 ns wr ? ale delay time t wl 80 ns wr width low t ww 215 ns m pd78c14(a) 34 serial operation: parameter symbol test condition min. max. unit sck cycle time t cyk sck input note 1 800 ns note 2 400 ns sck output 1.6 m s sck width low t kkl sck input note 1 335 ns note 2 160 ns sck output 700 ns sck width high t kkh sck input note 1 335 ns note 2 160 ns sck output 700 ns rxd setup time to sck t rxk note 1 80 ns rxd hold time after sck t krx note 1 80 ns sck ? ? txd delay time t ktx note 1 210 ns notes 1. in case of x1 clock rate in asynchronous mode, synchronous mode, or i/o interface mode. 2. in case of x16 or x64 clock rate in asynchronous mode. remark the numeric values in the table apply when f xx = 15 mhz, c l = 150 pf. zero-cross characteristics: parameter symbol test condition min. max. unit zero-cross detection input v zx ac coupled 1 1.8 vac pCp zero-cross accuracy a zx 60-hz sine wave 135 mv zero-cross detection input frequency f zx 0.05 1 khz other operation: parameter symbol test condition min. max. unit ti width high, low t tih , t til 6 t cyc ci width high, low t ci1h , t ci1l event counter mode 6 t cyc t ci2h , t ci2l pulse width measurement mode 48 t cyc nmi width high, low t nih , t nil 10 m s int1 width high, low t i1h , t i1l 36 t cyc int2 width high, low t i2h , t i2l 36 t cyc an7-4 width high, low t anh , t anl 36 t cyc reset width high, low t rsh , t rsl 10 m s m pd78c14(a) 35 2.2 v v dd ?1.0 v 0.45 v 0.8 v 2.2 v 0.8 v test points a/d converter characteristics: (t a = C40 to +85 ?c, v dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd , 3.4 v v aref av dd ) parameter symbol test condition min. typ. max. unit resolution 8 bits absolute accuracy note 3.4 v v aref av dd , 66 ns t cyc 170 ns 0.8 % fsr 4.0 v v aref av dd , 66 ns t cyc 170 ns 0.6 % fsr t a = C10 to +70 ?c, 0.4 % fsr 4.0 v v aref av dd , 66 ns t cyc 170 ns conversion time t conv 66 ns t cyc 110 ns 576 t cyc 110 ns t cyc 170 ns 432 t cyc sampling time t samp 66 ns t cyc 110 ns 96 t cyc 110 ns t cyc 170 ns 72 t cyc analog input voltage v ian an7-0 (include unused pins) 0 v aref v analog input impedance r an 50 m w reference voltage v aref 3.4 av dd v v aref current i aref1 operation mode 1.5 3.0 ma i aref2 stop mode 0.7 1.5 ma av dd supply current ai dd1 operation mode, f xx = 15 mhz 0.5 1.3 ma ai dd2 stop mode 10 20 m a note except quantization error (i.e. 1/2 lsb). ac timing test points * m pd78c14(a) 36 ac characteristic calculating expression depending on t cyc symbol calculating expression min./max. unit t al 2t C 100 min. ns t la t C 30 min. ns t ar 3t C 100 min. ns t ad 7t C 220 max. ns t ldr 5t C 200 max. ns t rd 4t C 150 max. ns t lr t C 50 min. ns t rl 2t C 50 min. ns t rr 4t C 50 (data read) min. ns 7t C 50 (op code fetch) t ll 2t C 40 min. ns t ml 2t C 100 min. ns t lm t C 30 min. ns t il 2t C 100 min. ns t li t C 30 min. ns t aw 3t C 100 min. ns t ldw t + 110 max. ns t lw t C 50 min. ns t dw 4t C 100 min. ns t wdh 2t C 70 min. ns t wl 2t C 50 min. ns t ww 4t C 50 min. ns t cyk 6t (sck input) note 1 /12t (sck input) note 2 min. ns 24t (sck output) t kkl 2.5t + 5 (sck input) note 1 /5t + 5 (sck input) note 2 min. ns 12t C 100 (sck output) t kkh 2.5t + 5 (sck input) note 1 /5t + 5 (sck input) note 2 min. ns 12t C 100 (sck output) notes 1. in case of x16 or x64 clock rate in asynchronous mode. 2. in case of x1 clock rate in asynchronous mode, synchronous mode, or i/o interface mode. remarks 1. t = t cyc = 1/f xx 2. symbols that cannot be found in this table do not depend on the oscillation frequency (f xx ). m pd78c14(a) 37 t cyc t ad t ll t la t ldr t rdh t rl t rr t rd t afr t lr t ar t al t lm t li t ml t il x1 pf7-0 pd7-0 ale rd mode1 (m1) note 1 mode0 ( io/m ) note 2 address (high-order) address (low-order) read data timing waveform read operation write operation notes 1. m1 signal is output to mode1 pin at first op code fetch cycle if mode1 pin is pulled up. 2. io/m signal is output to mode0 pin at sr to sr2 register read cycle if mode0 pin is pulled up. 3. io/m signal is output to mode0 pin at sr to sr2 register write cycle if mode0 pin is pulled up. t ll t la t dw t wdh t wl t ww t wd t lw t aw t al t li t il x1 pf7-0 pd7-0 ale wr mode0 ( io/m ) note 3 address (high-order) write data t ldw address (low-order) m pd78c14(a) 38 t til ti t tih serial operation timer input timing timer/event counter input timing t kkl t kkh t cyk t krx sck t x d r x d t ktx t rxk t ci1l ci t ci2l ci t ci2h event counter mode pulse width measurement mode t ci1h m pd78c14(a) 39 interrupt input timing reset input timing external clock timing t nil nmi t nih t i2l int2 t i2h int1 t i1h t i1l x1 t f h 0.8v dd 0.8 v t t t f l t cyc r f t rsl reset t rsh 0.8v dd 0.2v dd m pd78c14(a) 40 data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 ?c) parameter symbol test condition min. typ. max. unit data retention power supply voltage v dddr 2.5 5.5 v data retention power supply current i dddr v dddr = 2.5 v 1 15 m a v dddr = 5 v 10 % 10 50 m a v dd rise, fall time t rvd , t fvd 200 m s stop setup time to v dd t sstvd 12t note + 0.5 m s stop hold time to v dd t hvdst 12t note + 0.5 m s note t = t cyc = 1/f xx data retention timing * v dd stop t fvd t sstvd v dddr t rvd t hvdst v ih2 v il2 90 % 10 % m pd78c14(a) 41 6. characteristic curves (reference value) 0 4.5 5.0 5.5 6.0 10 15 20 i dd1 (typ.) i dd1 , i dd2 vs v dd (t a = 25 ?c, f xx = 15 mhz) supply voltage v dd [v] v dd supply current i dd1 , i dd2 [ma] i dd1 (typ.) 0 5 10 15 0 10 20 i dd1 , i dd2 vs f xx (t a = 25 ?c, v dd = 5 v) oscillation fre q uenc y f xx [ mhz ] v dd supply current i dd1 , i dd2 [ma] 0 5 25 30 i dd2 (typ.) 30 i dd2 (typ.) m pd78c14(a) 42 0 0.1 0.2 0.3 0.4 1.0 1.5 2.0 typ. i ol vs v ol (t a = 25 ?c, v dd = 5 v) output low voltage v ol [v] output low current i ol [ma] 0 0.5 2.5 0.5 0 0.1 0.2 0.3 0.4 ?1.0 ?1.5 typ. i oh vs v oh (t a = 25 ?c, v dd = 5 v) suppl y volta g e ?output hi g h volta g e v dd ?v oh [v] output high current i oh [ma] 0 ?0.5 0.5 m pd78c14(a) 43 0 2345 4 6 8 typ. i dddr vs v dddr (t a = 25 ?c) data retention supply volta g e v dddr [v] data retention supply current i dddr [ a] 0 2 10 6 m m pd78c14(a) 44 7. package drawings h i m c p a 64 132 33 m n j k s w x p64gq-100-36 item millimeters inches a c h i j k m n p s w 1.27 (t.p.) 0.25 16.5 0.100 (t.p.) 0.050 (t.p.) 0.010 0.157 1.634 note x 4.0 0.750 each lead centerline is located within 0.25 mm (0.010 inch) of its true position (t.p.) at maxi- mum material condition. 0.142 0.043 0.020 24.13 0.950 0.010 0.25 2.54 (t.p.) +0.004 ?.005 +0.011 ?.006 +0.012 ?.008 +0.004 ?.005 41.5 +0.3 ?.2 0.50 +0.10 1.1 +0.25 ?.15 +0.10 ?.05 +0.3 3.6 +0.1 +1.05 19.05 +1.05 0.650 +0.004 ?.003 +0.013 ?.012 +0.042 +0.042 64 pin plastic quip m pd78c14(a) 45 n a m f b 51 52 32 k l 64 pin plastic qfp (14 20) 64 1 20 19 33 p d c detail of lead end s q 55 g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 m pd78c14(a) 46 p68l-50a1-2 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. +0.007 ?.006 a b c d e f g h i j k m n p q t u 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 min. 3.4 1.27 (t.p.) 0.40 1.0 0.12 23.12 0.20 0.15 r 0.8 0.20 +0.10 ?.05 0.992 0.008 0.953 0.953 0.992 0.008 0.076 0.024 0.173 0.110 0.035 min. 0.134 0.050 (t.p.) 0.016 0.005 0.910 0.006 r 0.031 0.008 +0.009 ?.008 +0.009 ?.008 +0.004 ?.005 +0.004 ?.002 +0.009 ?.008 n k m q a u 68 b d c 1 f e t p m g h ij 68 pin plastic qfj ( 950 mil) m pd78c14(a) 47 8. recommended soldering conditions solder the m pd78c14(a) under the recommended conditions listed below. for details of the recommended conditions for soldering, please refer to semiconductor device mounting technology manual (iei-1207) . consult an nec sales representative about soldering methods and soldering conditions other than listed below. table 8-1. soldering conditions for surface mount type (1) m pD78C14Gf(a)-xxx-3be: 64-pin plastic qfp (14 x 20 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 ?c, time: within 30 s (at 210 ?c or higher), ir35-00-2 count: twice or less m pd78c14(a) 48 table 8-2. soldering conditions for hole-through type m pD78C14G(a)-xxx-36: 64-pin plastic quip soldering method soldering conditions wave soldering (pin part only) soldering bath temperature: 260 ?c or less, time: within 10 s partial heating pin temperature: 300 ?c or less, time: within 3 s (per pin row) caution apply wave soldering only to pins and be careful not to bring solder directly in contact with the package. m pd78c14(a) 49 appendix development tools the following development tools are provided for system development using the m pd78c14(a): language processor 87ad series this relocatable assembler is a program which converts a program written in mnemonics relocatable assembler into object code that can be executed by microcontroller. (ra87) in addition, it contains the automatic function of symbol table generation and branch instruction optimization processing. host machine ordering code os distribution media (product name) pc-9800 series ms-dos tm 3.5-inch 2hd m s5a13ra87 (ver. 2.11 to ver. 5.00a note ) 5-inch 2hd m s5a10ra87 ibm pc/at tm pc dos tm 3.5-inch 2hc m s7b13ra87 (ver. 3.1) 5-inch 2hc m s7b10ra87 prom write tools hard- pg-1500 pg-1500 is a prom programmer which enables you to program single chip microcontrollers ware containing prom by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to pg-1500. it also enables you to program typical prom devices of 256 kbits to 4 mbits. pa-78cp14gq prom programmer adapter for the m pd78cp14(a) and connected to pg-1500 for use. soft- pg-1500 pg-1500 and a host machine are connected by a serial or parallel interface and pg-1500 is ware controller controlled on the host machine. host machine ordering code os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 (ver. 2.11 to ver. 5.00a note ) 5-inch 2hd m s5a10pg1500 ibm pc/at pc dos 3.5-inch 2hd m s7b13pg1500 (ver. 3.1) 5-inch 2hc m s7b10pg1500 note ver. 5.00/500a have task swap function. however, this function is not supported by this software. remark operations of the assembler and pg-1500 controller are guaranteed only on the host machines under the operating systems listed above. * m pd78c14(a) 50 debugging tools in-circuit emulator (ie-78c11-m) is provided for m pd78c14(a) program debugging tools. the system configuration is listed below: hard- ie-78c11-m ie-78c11-m is an in-circuit emulator for the 87ad series. ware ie-78c11-m can be connected to a host machine efficient debugging. soft- ie-78c11-m ie-78c11-m and a host machine are connected by rs-232-c and ie-78c11-m is controlled ware control program on the host machine. (ie controller) host machine ordering code os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie78c11 (ver. 2.11 to ver. 3.30d) 5-inch 2hd m s5a10ie78c11 ibm pc/at pc dos 5-inch 2hc m s7b10ie78c11 (ver. 3.1) remark operation of ie controller is guaranteed only on the host machine under the operating systems listed above. m pd78c14(a) 51 notes for cmos devices (1) precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. (2) handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. m pd78c14(a) 52 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. |
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